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| 1. general description the device is an sd 3.0-compliant 6-bit bidirectional dual voltage level translator. it is designed to interface between a memory card op erating at 1.8 v or 2. 9 v signal levels and a host with a fixed nominal supply voltage of 1.2 v to 3.3 v. the device supports sd 3.0 sdr50, ddr50, sdr25, sdr12 and sd 2.0 high-speed (50 mhz) and default-speed (25 mhz) modes. the device has an integrated switchable voltage regulator to supply the card-side i/os, built-in emi filters and robust esd protections (iec 61000-4-2, level 4). 2. features and benefits ? supports up to 100 mhz clock rate ? feedback channel for clock synchronization ? sd 3.0 specification-compliant voltage translation to support sdr50, ddr50, sdr25, sdr12, high-speed and default-speed modes ? low dropout voltage regulator to supply the card-side i/os ? low power consumption by push-pull output stage with break-before-make architecture ? integrated pull-up and pull-down resistors: no external resistors required ? integrated emi filters suppress higher harmonics of digital i/os ? integrated 8 kv esd protection according to iec 61000-4-2, level 4 on card side ? level shifting buffers keep esd stress away from the host (zero-clamping concept) ? pb-free, rohs compliant and free of ha logen and antimony (dark green compliant) ? 25-ball wlcsp; pitch 0.4 mm 3. applications sd, mmc or microsd memory card interfaces in portable electronic applications supporting different interface voltage modes of the sd 3.0 specification, such as mobile and smart phone, digital camera and card reader in (laptop) computer. 4. ordering information [1] size 2.04 ? 2.04 ? 0.5 mm IP4855CX25 sd 3.0-compliant memory card integrated voltage level translator with emi filt er and esd protection rev. 1 ? 13 september 2012 product data sheet table 1. ordering information type number package name description version IP4855CX25/p wlcsp25 wafer level chip-size package; 25 bumps (5 ? 5) IP4855CX25
IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 2 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 5. block diagram fig 1. application diagram ! ! ! IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 3 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 6. functional diagram fig 2. functional diagram ""# ! ! ! !! ! !$ ! ! !% $ !& % ! ! !' & ' ! % $ IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 4 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 7. pinning information 7.1 pinning 7.2 pin description fig 3. pin configuration wlcsp25 table 2. pin allocation table pin symbol pin symbol pin symbol pin symbol pin symbol a1 data2_h a2 dir_cmd a3 dir_0 a4 v supply a5 data2_sd b1 data3_h b2 sel b3 v cca b4 v ldo b5 data3_sd c1 clk_in c2 enable c3 gnd c4 v sd_ref c5 clk_sd d1 data0_h d2 cmd_h d3 cd d4 cmd_sd d5 data0_sd e1 data1_h e2 clk_fb e3 dir_1_3 e4 wp e5 data1_sd 008aaa193 transparent top view, solder balls facing down d b e c a 24 135 bump a1 index area table 3. pin description symbol [1] pin type [2] description data2_h a1 i/o data 2 input or output on host side dir_cmd a2 i direction control input for command dir_0 a3 i direction control input for data 0 v supply a4 s supply voltage (from battery or regulator) data2_sd a5 i/o data 2 input or output on memory card side data3_h b1 i/o data 3 input or output on host side sel b2 i card side i/o voltage level select v cca b3 s supply voltage from host side v ldo b4 o internal supply decoupling data3_sd b5 i/o data 3 input or output on memory card side IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 5 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator [1] the pin names relate particularly to sd memory cards, but also apply to microsd and mmc memory cards. [2] i = input, o = output, i/o = input and output, s = power supply 8. functional description 8.1 level translator the bidirectional level translator shifts the data between the i/o supply levels of the host and the memory card. dedicated direction co ntrol signals determine if a command and data signals are transferred from the memory card to the host (card read mode) or from the host to the memory card (card write mode). the voltage translator has to support several clock and data transfer rates at the signaling levels specified in the sd 3.0 standard specification. clk_in c1 i clock signal input on host side enable c2 i device enable input gnd c3 s supply ground v sd_ref c4 i reference voltage for the internal voltage regulator clk_sd c5 o clock signal output on memory card side data0_h d1 i/o data 0 input or output on host side cmd_h d2 i/o command input or output on host side cd d3 o card detect switch biasing output cmd_sd d4 i/o command input or output on memory card side data0_sd d5 i/o data 0 input or output on memory card side data1_h e1 i/o data 1 input or output on host side clk_fb e2 o clock feedback output on host side dir_1_3 e3 i direction control input for data 1, data 2, data 3 wp e4 o write protect switch biasing output data1_sd e5 i/o data 1 input or output on memory card side table 3. pin description ?continued symbol [1] pin type [2] description table 4. supported modes bus speed mode signal level (v) clock rate (mhz) data rate (mb/s) default-speed 3.3 25 12.5 high-speed 3.3 50 25 sdr12 1.8 25 12.5 sdr25 1.8 50 25 sdr50 1.8 100 50 ddr50 1.8 50 50 IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 6 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 8.2 enable and direction control the pin enable enables/disables the low dropout (ldo) and is used to put the host-side, card-side i/o drivers into high-ohmic 3-state mode. [1] h = high; l = low and x = irrelevant. 8.3 integrated voltage regulator the low dropout voltage regulator delivers supply voltage for the voltage translators and the card-side input/output stages. it has to support 1.8 v and 3 v signaling modes as stipulated in the sd 3.0 specification. the s witching time between the two output voltage modes is compliant with sd 3.0 specification. depending on the signaling level at pin sel, the regulator delivers 1.8 v (sel = high) or 2.9 v (sel = low, v sd_ref <1 v). for card supply voltage, see section 8.4 . [1] h = high and l = low. [2] host-side pins are not influenced by sel. table 5. i/o function control signal truth table control host-side memory card-side pin level [1] pin function pin function pin enable = high and v cca ? 1.62 v dir_cmd h cmd_h input cmd_sd output l cmd_h output cmd_sd input dir_0 h data0_h input data0_sd output l data0_h output data0_sd input dir_1_3 h data1_h data2_h data3_h input data1_sd data2_sd data3_sd output ldata1_h data2_h data3_h output data1_sd data2_sd data3_sd input - - clk_in input clk_sd output - - clk_fb output - - pin enable = low or v cca ? 0.8 v dir_cmd x cmd_h high-ohmic cmd_sd high-ohmic dir_0 x data0_h high-ohmic data0_sd high-ohmic dir_1_3 x data1_h data2_h data3_h high-ohmic data1_sd data2_sd data3_sd high-ohmic - - clk_in input clk_sd high-ohmic - - clk_in high-ohmic - - table 6. sd card side voltage level control signal truth table input output sel [1] v sd_ref v ldo pin [2] function h irrelevant 1.8 v data0_sd to data3_sd, clk_sd low supply voltage level (1.8 v typ ) l < 1 v 2.9 v data0_sd to data3_sd, clk_sd high supply voltage level (2.9 v typ ) >1.5v v sd_ref data0_sd to data3_sd, clk_sd supply voltage level based on v sd_ref IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 7 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 8.4 memory card voltage tr acking (reference select) the device can track the memory card supply via pin v sd_ref . this allows achieving optimum interoperability by perfectly matching input/output leve ls between voltage translator and memory card in the 3 v signaling mode. therefore, the voltage regulator aims to follow the reference voltage provided at input v sd_ref directly . if tracking of the memory card supply is not desired, connect pin v sd_ref to ground so the voltage regulator refers to an integrated voltage reference. for 1.8 v (sel = high) signaling, the voltage regulator is referred to the internal reference which is independent of the voltage at v sd_ref. 8.5 feedback clock channel the clock is transmitted from the host to the memory card side. the voltage translator and the printed-circuit board (pcb) tracks introduce some amount of delay. it reduces timing margin for data read back from memory card, es pecially at higher data rates. therefore, a feedback path is provided to compensate the delay. the reasoning behind this approach is the fact that the clock is always delivered by the host, while the data in the timing critical read mode comes from the card. 8.6 emi filter all input/output driver stages are equipped with emi filters to reduce interferences towards sensitive mobile communication. 8.7 esd protection the device has robust esd protections on all memory card pins as well as on the v sd_ref and v supply pins. the architecture prevents any stress for the host: the voltage translator discharges any stress to supply ground. pins write protect (wp) and card detection (cd) might be pulled down by the memory card which has to be detected by the host. bo th signals must be high if no card is inserted. therefore the pins are equipp ed with internationa l electrotechnical commission (iec) system-level esd protection s and pull-up resistors connected to the host supply v cca . IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 8 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 9. limiting values [1] all system level tests are performed with the applicati on-specific capacitors connected to the supply pins v supply , v ldo and v cca . 10. recommended operating conditions [1] by minimum value the device is still fu lly functional, but the voltage on pin v ldo might drop below the recommended memory card supply voltage. [2] the voltage must not exceed 3.6 v. table 7. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage 4 ms transient on pin v supply ? 0.5 +6.0 v on pin v cca ? 0.5 +4.6 v v i input voltage 4 ms transient at i/o pins ? 0.5 +4.6 v p tot total power dissipation t amb = ? 40 ? c to +85 ?c - 1000 mw t stg storage temperature ? 55 +150 ?c t amb ambient temperature ? 40 +85 ?c v esd electrostatic discharge voltage iec 61000-4-2, level 4, all memory card-side pins, v supply , v sd_ref , wp and cd to ground [1] ? 8000 +8000 v human body model (hbm) jedec jesd22-a114f; all pins ? 2000 +2000 v machine model (mm) jedec jesd22-a115; all pins ? 200 +200 v i lu(io) input/output latch-up current jesd 78b: ? 0.5 v cc IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 10 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator [1] typical values are measured at t amb =25 ? c. [2] emi filter line capacitance per data channel from i/o driver to pin; c ch is guaranteed by design. host-side output signals: clk_fb, cmd_h and data0_h to data3_h v oh high-level output voltage i o =2ma; v i =v ih (card side) 0.75 ? v cca -v v ol low-level output voltage i o = ? 2 ma; v i =v il (card side) - - 0.125 ? v cca v card-side input signals: cmd_sd and data0_sd to data3_sd v ih high-level input voltage sel = low (2.9 v interface) 0.625 ? v o(reg) -v o(reg) + 0.3 v sel = high (1.8 v interface) 0.625 ? v o(reg) -v o(reg) + 0.3 v v il low-level input voltage sel = low (2.9 v interface) ? 0.3 - 0.25 ? v o(reg) v sel = high (1.8 v interface) ? 0.3 - 0.25 ? v o(reg) v card-side output signal cmd_sd and data0_sd to data3_sd, clk_sd v oh high-level output voltage i o = ? 4ma; v i =v ih (host side); sel = low (2.9 v interface) 0.75 ? v o(reg) -v o(reg) + 0.3 v i o = ? 2ma; v i =v ih (host side); sel = high (1.8 v interface) 0.75 ? v o(reg) -v o(reg) + 0.3 v v ol low-level output voltage i o =4ma; v i =v il (host side); sel = low (2.9 v interface) ? 0.3 - 0.125 ? v o(reg) v i o =2ma; v i =v il (host side); sel = high (1.8 v interface) ? 0.3 - 0.125 ? v o(reg) v i o(sc) short-circuit output current card-side pins connected to ground; host-side input signals = high; v sd_ref =3.6v; v supply =5.5v; v cca = 3.6 v; sel = low; dir_1_3, dir_cmd, dir_0 = high - - 100 ma bus signal equivalent capacitance c ch channel capacitance v i =0v; f i = 1 mhz; v supply =3.5v; v cca =1.8v [2] host side - 3.5 5 pf card side - 5 10 pf current consumption i cc(stat) static supply current enable = high (active mode); all inputs = high; dir = low sel = low (2.9 v interface) - - 100 ? a sel = high (1.8 v interface) - - 100 ? a i cc(stb) standby supply current enable = low (inactive mode) - - 1 ? a table 10. static characteristics ?continued at recommended operating conditions; t amb = ? 40 ? c to +85 ? c; voltages are referenc ed to gnd (ground = 0 v); c ext =1 ? f at pin v ldo ; unless otherwise specified. symbol parameter conditions min typ [1] max unit IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 11 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 12. dynamic characteristics 12.1 voltage regulator table 11. voltage regulator t amb =25 ? c; unless otherwise specified. symbol parameter conditions min typ max unit voltage regulator output pin: v ldo t startup(reg) regulator start-up time v cca =1.8v; v supply = 3.5 v; c ext =1 ? f; see figure 5 - - 100 ? s t f(o) output fall time v o(reg) = 2.9 v to 1.8 v; sel = low to high; see figure 4 --1ms t r(o) output rise time v o(reg) = 1.8 v to 2.9 v; sel = high to low; see figure 4 - - 100 ? s fig 4. regulator mode change timing measuring points: enable signal at 0.5 v cca and regulator output signal at 0.97 v o(reg) . fig 5. regulator start-up time "# #'( % ( % ( "# "# "# "# " "# "# "# )!* + " " " " " " %,-.,/0"1 2 3.41 % , " " " " 2 5.41 001aah981 v i gnd 97 % 50 % t startup(reg) v o(reg) regulator output enable 0 v IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 12 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 12.2 esd characteristic of pin write protect and card detect [1] tlp according to ansi-esd stm5.5.1/iec 62615 z o =50 ? ; pulse width = 100 ns; rise time = 200 ps; averaging window = 50 ns to 80 ns 13. application information the IP4855CX25 is optimized to connect sd 3.0 and sd 2.0 compatible memory cards to 1.8 v base band/host interfaces. while the internal i/o interface towards the memory card is supplied by the IP4855CX25 integrated voltage regulator, any connected memory card has to be supplied from an external sour ce. using for example ddr50 or sdr50 modes requires a power supply with up to 400 ma dc current capabilities. place IP4855CX25 as close as possible to the card holder to minimize the influence of trace length on the timing values. the tr ace length between IP4855CX25 and the card has a much bigger influence on the timing than the identical length between the host interface and the IP4855CX25. table 12. esd characteristic of write protect and card detect at recommended operating conditions; t amb =+25 ? c; voltages are referenced to gnd (ground = 0 v); unless otherwise specified symbol parameter conditions min typ max unit esd protection pins: wp and cd v br breakdown voltage tlp; i = 1 ma - 8 - v r dyn dynamic resistance positive transient [1] -0.5- ? negative transient [1] -0.5- ? IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 13 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator one main task of the level translator is to sh ift the signal within the sd 3.0 specification. therefore, the following simulation results sh ow the low impact of the device. use the clock feedback channel for a compensation of delay introduced by pcb traces and IP4855CX25. fig 6. IP4855CX25 application diagram and output driver structure ! ! ! 672 45 45 "$ , -668929-:662 3458629/;- <9-/=>?-:@>?;;85/a65 /,>;6,60292/40 @ IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 14 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 13.1 simulation setup for transiti on time, propagation delay and set-up/hold times a. host-side to card-side simulation setup b. card-side to host-side simulation setup fig 7. timing simulation setup <9-/=-/0b;6=:9006;-/,?;92/40,486; =:9006; 56-/-290=6 ;498 =9>9=/290=6 =958-/86 :4-2-/86 8/56=2/40c 259=6;60b2: ,,24 ,, 59=6/,>6890=6%d24&%de/2:04,/09;a9;?6!%d <9-/=-/0b;6=:9006;-/,?;92/40,486; =:9006; 56-/-290=6 =958-/86 :4-2-/86 8/56=2/40c ;498 =9>9=/290=6 259=6;60b2: ,,24 ,, 59=6/,>6890=6%d24&%de/2:04,/09;a9;?6!%d fig 8. output rise and fall times 2 2 2 2 ( ( # ( ' ( IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 15 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator fig 9. set-up, hold and output delay timing 4?2>?286;9f2/,6 -62@?>2/,6 )!* + )!* + :4;82/,6 IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 16 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 13.2 interface voltage timing data table 13. output rise and fall times card side v supply = 4 v; unless otherwise specified; track impedance 35 ? , track length (to and from IP4855CX25) 15 mm; r source =50 ? ; see figure 7 for set-up circuit and figure 8 for timing diagram; v cca = 1.8 v; transition time is the same as output rise time and output fall time symbol parameter conditions min. typ max unit memory card-side output pins: clk_sd, cmd_sd an d data0_sd to data3_sd; 2.9 v mode (sel = low) reference points at 20 % and 70 % t t transition time c l =10pf nominal case; t amb =+25 ?c; v ldo = 2.9 v 0.8 1.1 1.3 ns best case; t amb = ? 40 ?c; v ldo = 3.6 v 0.8 1.0 1.2 ns worst case; t amb = +85 ?c; v ldo = 2.7 v 0.8 1.1 1.3 ns c l =20pf [1] nominal case; t amb = +25 ?c; v ldo = 2.9 v 1.4 1.6 1.9 ns best case; t amb = ? 40 ?c; v ldo = 3.6 v 1.3 1.6 1.8 ns worst case; t amb = +85 ?c; v ldo = 2.7 v 1.4 1.6 1.9 ns reference points at 10 % and 90 % [2] t t transition time c l =10pf nominal case; t amb = +25 ?c; v ldo = 2.9 v 1.9 2.1 2.4 ns best case; t amb = ? 40 ?c; v ldo = 3.6 v 1.9 2.0 2.2 ns worst case; t amb = +85 ?c; v ldo = 2.7 v 2.0 2.2 2.4 ns c l = 20 pf [1] nominal case; t amb = +25 ?c; v ldo = 2.9 v 2.9 3.1 3.4 ns best case; t amb = ? 40 ?c; v ldo = 3.6 v 2.9 3.0 3.2 ns worst case; t amb = +85 ?c; v ldo = 2.7 v 2.9 3.2 3.5 ns memory card-side output pins: cl k_sd, cmd_sd and data0_sd to da ta3_sd; 1.8 v mode (sel = high) reference points at 20 % and 70 % t t transition time c l = 10 pf nominal case; t amb = +25 ?c; v ldo = 1.8 v 0.8 1.1 1.3 ns best case; t amb = ? 40 ?c; v ldo = 1.95 v 0.8 1.0 1.2 ns worst case; t amb = +85 ?c; v ldo = 1.7 v 0.8 1.1 1.3 ns t t transition time c l = 20 pf [1] nominal case; t amb = +25 ?c; v ldo = 1.8 v 1.4 1.6 1.9 ns best case; t amb = ? 40 ?c; v ldo = 1.95 v 1.3 1.6 1.8 ns worst case; t amb = +85 ?c; v ldo = 1.7 v 1.4 1.6 1.9 ns reference points at 10 % and 90 % [2] t t transition time c l = 10 pf nominal case; t amb = +25 ?c; v ldo = 1.8 v 1.9 2.1 2.4 ns best case; t amb = ? 40 ?c; v ldo = 1.95 v 1.9 2.0 2.2 ns worst case; t amb = +85 ?c; v ldo = 1.7 v 2.0 2.2 2.4 ns IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 17 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator [1] a capacitive load of c l = 20 pf is out of the range of allowed sd-card interface parasitic capacitance. [1] reference points 90 % and 10 % are not required according to the sd 3.0 specification. t t transition time c l = 20 pf [1] nominal case; t amb = +25 ?c; v ldo = 1.8 v 2.9 3.1 3.4 ns best case; t amb = ? 40 ?c; v ldo = 1.95 v 2.9 3.0 3.2 ns worst case; t amb = +85 ?c; v ldo = 1.7 v 2.9 3.2 3.5 ns table 13. output rise and fall times card side ?continued v supply = 4 v; unless otherwise specified; track impedance 35 ? , track length (to and from IP4855CX25) 15 mm; r source =50 ? ; see figure 7 for set-up circuit and figure 8 for timing diagram; v cca = 1.8 v; transition time is the same as output rise time and output fall time symbol parameter conditions min. typ max unit table 14. output rise and fall times host side v supply = 4.0 v; sel = low; v o(reg) = 2.9 v; unless otherwise spec ified; track impedance 35 ? , track length (to and from IP4855CX25) 15 mm; r source =50 ? ; see figure 7 for set-up circuit and figure 8 timing diagram; transition time is the same as ou tput rise time and output fall time symbol parameter conditions min typ max unit host-side output pins: cl k_fb, cmd_h and data0_h to data3_h (3.3 v host) reference points at 20 % and 70 % t t transition time c l = 5 pf nominal case; t amb = +25 ?c; v cca = 3.3 v 0.5 0.6 0.7 ns best case; t amb = ? 40 ?c; v cca = 3.6 v 0.5 0.6 0.7 ns worst case; t amb = +85 ?c; v cca = 2.7 v 0.5 0.6 0.7 ns reference points at 10 % and 90 % [1] t t transition time c l =5pf nominal case; t amb = +25 ?c; v cca = 3.3 v 1.0 1.3 1.5 ns best case; t amb = ? 40 ?c; v cca = 3.6 v 1.0 1.2 1.4 ns worst case; t amb = +85 ?c; v cca = 2.7 v 1.3 1.4 1.6 ns host-side output pins: cl k_fb, cmd_h and data0_h to data3_h (1.8 v host) reference points at 20 % and 70 % t t transition time c l = 5 pf nominal case; t amb = +25 ?c; v cca = 1.8 v 0.5 0.6 0.7 ns best case; t amb = ? 40 ?c; v cca = 1.9 v 0.5 0.6 0.7 ns worst case; t amb = +85 ?c; v cca = 1.62 v 0.5 0.6 0.7 ns reference points at 10 % and 90 % [1] t t transition time c l =5pf nominal case; t amb = +25 ?c; v cca = 1.8 v 1.0 1.3 1.5 ns best case; t amb = ? 40 ?c; v cca = 1.9 v 1.0 1.2 1.4 ns worst case; t amb = +85 ?c; v cca = 1.62 v 1.3 1.4 1.6 ns IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 18 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 13.3 ddr50 mode timing details the default-speed (ds) and high-speed (hs) modes use 3.3 v signaling and offer a maximum of 25 mb/s. besides these modes, IP4855CX25 also supports the sdr12, sdr25 and ddr50 modes using 1.8 v signaling and up to 50 mb/s. especially the ddr50 mode introduces a basic change in the timing behavior of the sd card interface. the sdr12 and sdr50 mo des are similar to the ds and hs modes. any delay on all relevant signal lines (as shown in the timing diagram in figure 10 ) is uncritical for sd card write operations as lo ng as the skew between the different signals is small enough. fig 10. ddr50 write timing diagram @ @ )!* + /0>?2 % e5/26,486 )!* + :4-24?2>?2 8929 /0a9;/8 8929 /0a9;/8 8929 /0a9;/8 8929 /0a9;/8 /0a9;/8 8929 /0a9;/8 2 .:4-2@-/86/0>?2-24 ,6,45f=958@-/864?2>?2-g c 1 @ @ )!* + h )!* + 8929 IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 19 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator in contrast to the write cycle, the read cycl e is more complex to analyze and depends on the IP4855CX25 delay, the maximum delay added by the pcb and the additional setup time of the sd card. the same mechanism is trig gered on each falling clock edge too, as the ddr50 mode uses both edges of the clock signal for data transfer. according to the sd 3.01 physical layer specification, the maximum delay between clk_in (clk_sd signal) at the sd card an d data out from the sd card (data[3:0]_sd out) is 7.0 ns. this value is specified for a load of c l ? 25 pf. table 15. ddr50 read mode: parameters fo r best case and worst case timings parameter best case timing ( figure 11 ) worst case timing ( figure 12 ) pcb output impedance z o 65 ? 25 ? symmetrical trace length 15 mm per side 100 mm per side t pd minimum maximum driver model fast slow IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 20 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator pcb z o =65 ? , trace length = 15 mm, t pd = minimum, fast driver model fig 11. detailed description of a dd r50 read cycle, best case timing @ @ 8929 /0a9;/8 8929 /0a9;/8 8929 /0a9;/8 8929 /0a9;/8 8929 /0a9;/8 8929 /0a9;/8 @ )!* + )!* + @ h 2 4-2@-/86>/0- 24 2 6,45f=958@-/86/0>?2-24 :4-2@-/864?2>?2- 2 7 ?2>?286;9f2/,68?5/0b89292590-365,486" 66 >:f-/=9;;9f65->6=/3/=92/403458629/;-" .:4-21 )!* + 4?2>?2 )!* + :4-2/0>?2 2 h.,971 !"!0- '" 0- "0- " 0- 395/-/0b68b643 /-?-682425/bb65 95698i2:69=2?9;8929/-5698/0242:6:4-2 402:634;;4e/0b39;;/0b 68b6" % 5698,486i<6-2=9-62/,/0b . 1 . 1 .1 .!1 .!1 . 1 . 1 .1 .1 .!1 .$1 .!1 .$1 .$1 IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 21 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator pcb z o =25 ? , trace length = 100 mm, t pd = maximum, slow driver model fig 12. detailed description of a ddr50 read cycle, worst case timing /0a9;/8 /0a9;/8 @ @ 8929 /0a9;/8 /0a9;/8 /0a9;/8 8929 8929 8929 8929 @ @ h 2 4-2@-/86>/0- 24 2 6,45f=958@-/86/0>?2-24 :4-2@-/864?2>?2- 2 7 ?2>?286;9f2/,68?5/0b89292590-365,486" 66 >:f-/=9;;9f65->6=/3/=92/403458629/;-" .:4-21 )!* + 4?2>?2 )!* + :4-2/0>?2 2 h.,971 '" 0- 395/-/0b68b643 /-?-682425/bb6 5 95698i2:69=2?9;8929/-5698/0242:6:4- 2 402:634;;4e/0b39;;/0b 68b6" % 5698,486ie45-2=9-62/,/0b "!0- %"#0- &"&0- 8929 /0a9;/8 )!* + )!* + . 1 . 1 .1 .!1 .!1 . 1 . 1 .1 .1 .!1 .$1 .!1 .$1 .$1 IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 22 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 14. test information definitions test circuit: r source = source resistance of pulse generator. r term = termination resistance shoul d be equal to output impedance z o of pulse generator. c l = load capacitance includi ng jig and probe capacitance. r l = load resistance. fig 13. load circuitry for measuring switching time % ( % ( >?;-6e/82: ( ' ( 06b92/a6 /0>?2 >4-/2/a6 /0>?2 % ( % ( ' ( ( 2 3.41 2 5.41 2 5.41 2 3.41 265, -4?5=6 % d >?;-6e/82: IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 23 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 15. package outline fig 14. package outline IP4855CX25 (wlcsp25) wlcsp25_5x5_po european projection wlcsp25: wafer level chip-size package; 25 bumps (5 x 5) bump a1 index area d e x detail x a a 2 a 1 e 1 e 1 e e b e d c b a 12345 table 16. dimensions of IP4855CX25 for figure 14 symbol min typ max unit a 0.44 0.47 0.50 mm a 1 0.18 0.20 0.22 mm a 2 0.25 0.27 0.29 mm b 0.21 0.26 0.31 mm d 1.99 2.04 2.09 mm e 1.99 2.04 2.09 mm e- 0 . 4 - m m IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 24 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 16. design and asse mbly recommendations 16.1 pcb design guidelines for optimum performance, use a non-solder mask pcb design (nsmd), also known as a copper-defined design, incorporating laser-dr illed micro-vias connecting the ground pads to a buried ground-plane layer. this results in the lowest possible ground inductance and provides the best high frequency and esd performance. for this case, refer to ta b l e 1 7 for the recommended pcb design parameters. [1] osp: organic solder ability preservation fr4: flame retard 4 16.2 pcb assembly guidelines for pb-free soldering table 17. recommended pcb design parameters parameter value or specification [1] pcb pad diameter 250 ? m micro-via diameter 100 ? m (0.004 inch) solder mask aperture diameter 325 ? m copper thickness 20 ? m to 40 ? m copper finish auni or osp pcb material fr4 table 18. assembly recommendations parameter value or specification solder screen aperture diameter 290 ? m solder screen thickness 100 ? m (0.004 inch) solder paste: pb-free snag (3 % to 4 %) cu (0.5 % to 0.9 %) solder/flux ratio 50/50 solder reflow profile see figure 15 IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 25 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 17. abbreviations the device can withstand at least three reflows of this profile. fig 15. pb-free solder reflow profile table 19. reflow soldering process characteristics symbol parameter conditions min typ max unit t reflow(peak) peak reflow temperature 230 - 260 ?c t 1 time 1 soak time 60 - 180 s t 2 time 2 time during t ? 250 ? c--30s t 3 time 3 time during t ? 230 ? c10- 50s t 4 time 4 time during t > 217 ? c 30 - 150 s t 5 time 5 - - 540 s dt/dt rate of change of temperature cooling rate - - ? 6 ?c/s pre-heat 2.5 - 4.0 ?c/s 001aai161 t reflow(peak) 250 230 217 t (c) cooling rate pre-heat t 1 t 2 t 5 t 4 t 3 t (s) table 20. abbreviations acronym description dut device under test emi electromagnet ic interference esd electrostatic discharge fr4 flame retard 4 mmc multimedia card nsmd non-solder mask design osp organic solderability preservation pcb printed-circuit board rohs restriction of hazardous substances sd secure digital wlcsp wafer-level chip-scale package IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 26 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 18. revision history table 21. revision history document id release date data sheet status change notice supersedes IP4855CX25 v.1 20120913 product data sheet - - IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 27 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator 19. legal information 19.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 19.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 19.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. IP4855CX25 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 13 september 2012 28 of 29 nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. quick reference data ? the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not comple te, exhaustive or legally binding. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 19.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 20. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors IP4855CX25 sd 3.0-compliant memory card integrated dual voltage level translator ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 13 september 2012 document identifier: IP4855CX25 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 functional description . . . . . . . . . . . . . . . . . . . 5 8.1 level translator . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.2 enable and direction control . . . . . . . . . . . . . . . 6 8.3 integrated voltage regulator . . . . . . . . . . . . . . . 6 8.4 memory card voltage tracking (reference select) . . . . . . . . . . . . . . . . . . . . . . . 7 8.5 feedback clock channel . . . . . . . . . . . . . . . . . . 7 8.6 emi filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.7 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 10 recommended operating conditions. . . . . . . . 8 11 static characteristics. . . . . . . . . . . . . . . . . . . . . 9 12 dynamic characteristics . . . . . . . . . . . . . . . . . 11 12.1 voltage regulator. . . . . . . . . . . . . . . . . . . . . . . 11 12.2 esd characteristic of pin write protect and card detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 application information. . . . . . . . . . . . . . . . . . 12 13.1 simulation setup for transition time, propagation delay and set-up/hold times . . . . . . . . . . . . . . 14 13.2 interface voltage timing data. . . . . . . . . . . . . . 16 13.3 ddr50 mode timing details . . . . . . . . . . . . . . 18 14 test information . . . . . . . . . . . . . . . . . . . . . . . . 22 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 16 design and assembly recommendations . . . 24 16.1 pcb design guidelines . . . . . . . . . . . . . . . . . . 24 16.2 pcb assembly guidelines for pb-free soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . 26 19 legal information. . . . . . . . . . . . . . . . . . . . . . . 27 19.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 27 19.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 19.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 19.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 28 20 contact information. . . . . . . . . . . . . . . . . . . . . 28 21 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 |
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